Modern high-density integrated circuits are vulnerable to damage from the electrostatic discharge (ESD) of a charged body as it physically contacts the integrated circuit. ESD damage occurs when the amount of charge exceeds the capability of a conduction path through the integrated circuit. A typical ESD failure mechanism includes thermal runaway resulting in junction shorting and dielectric breakdown resulting in gate-junction shorting. ESD can result from either automated or human handling. If the ESD voltage applied to a gate insulator is excessive the gate oxide can break down. Metal oxide semiconductor field effect transistor (MOSFET) devices are particularly vulnerable to ESD damage.
To avoid damage from ESD, integrated circuits typically incorporate ESD protection devices at each external terminal. ESD protection devices generally operate by providing a high capacity conduction path, so that brief but massive ESD charge may be safely conducted away from structures that are not capable of handling the discharge. Inputs and outputs typically have a separate ESD protection device added in parallel to the terminal.
There is a continuing drive in the semiconductor industry to fabricate devices exhibiting increased performance and decreased power consumption. Planar transistors, such as MOSFETs are particularly well suited for use in high density integrated circuits. As the size of MOSFETs and other devices decrease, the dimensions of source/drain regions, channel regions, and gate electrodes also decreases.
The miniaturization of planar transistors of short channel lengths require very shallow source/drain junctions to avoid lateral diffusion of implanted dopant which causes leakage currents and poor breakdown performance. Shallow source/drain junction, on the order of 1,000 Å or less, are generally required for acceptable performance of short channel devices. SOI technology allows the formation high-speed, shallow-junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance.
A SOI structure has semiconductor devices formed on a substrate in which a buried insulator region limits the depth of the active regions. SOI provides significant advantages over bulk technologies. Among its technological benefits, SOI provides reduced short channel effects, reduced electric field strength, reduced parasitic capacitance, higher speed and lower power consumption.
While SOI devices enable the production of higher density integrated circuits, SOI devices are more vulnerable to damage from ESD. The SOI layer is much thinner than a bulk silicon substrate and therefore, has lower current carrying capability and lower resistance to heating than bulk silicon substrates. ESD causes severe localized heating which can break down oxides and consequently damage SOI circuits. The buried oxide layer in a SOI device inhibits the conduction of heat away from the SOI circuits, leading to thermally induced damage of the SOI circuits.